Automatic compiler dataflow optimization to enable pipelining of loops with local storage requirements

ABSTRACT

Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).

COPYRIGHT NOTICE

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TECHNICAL FIELD

Embodiments generally relate to compilers. More particularly,embodiments relate to automatic compiler dataflow optimizations toenable pipelining of loops with local storage requirements.

BACKGROUND

Dataflow graphs may be used to model computer source code in terms ofthe dependencies between individual operations performed by the code. Acompiler may transform the source code into the dataflow graph, which istypically executed by accelerator hardware such as a field programmablegate array (FPGA), configurable spatial accelerator (CSA), or otherdataflow architecture. While the accelerator hardware may be useful whendealing with high performance computing (HPC) and/or data centerapplications that operate on relatively large data arrays andstructures, there remains considerable room for improvement. Forexample, if the operations of the source code involve the execution ofloops that internally declare “private” variables for large data arrays,the ability to hold (e.g., “registerize”) the underlying data in theinternal channels (e.g., communication arcs, buffers, latencyinsensitive channels/LICs, etc.) of the accelerator may be limited. As aresult, the private variables may be treated as purely memory-basedvariables, which may cause performance losses.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments will become apparent to oneskilled in the art by reading the following specification and appendedclaims, and by referencing the following drawings, in which:

FIG. 1 is a block diagram of an example of a compiler output accordingto an embodiment;

FIG. 2A is a source code listing of an example of a loop with fixed-sizelocal storage according to an embodiment;

FIG. 2B is a source code listing of an example of a loop withruntime-varying local storage according to an embodiment;

FIG. 2C is a source code listing of an example of a loop with anexplicitly designated private variable according to an embodiment;

FIG. 2D is a source code listing of an example of a loop with adynamically allocated local variable according to an embodiment;

FIG. 3 is a block diagram of an example of a communication arc in adataflow graph according to an embodiment;

FIG. 4 is a flowchart of an example of a method of operating a compileraccording to an embodiment;

FIG. 5 is a block diagram of an example of a compiler according to anembodiment;

FIG. 6 is a block diagram of an example of a performance-enhancedcomputing system according to an embodiment;

FIG. 7 is an illustration of an example of a semiconductor apparatusaccording to an embodiment;

FIG. 8 is a block diagram of an example of a processor according to anembodiment; and

FIG. 9 is a block diagram of an example of a multi-processor basedcomputing system according to an embodiment.

DESCRIPTION OF EMBODIMENTS

Turning now to FIG. 1, a compiler 20 is shown, where the compiler 20automatically transforms source code 22 into an output 24 that isexecutable by a dataflow architecture such as, for example, an FPGA,CSA, and so forth. In an embodiment, the source code 22 is written in ahigh-level language such as, for example, C, C++, or Fortran augmentedby parallel annotations (e.g., OpenMP parallel pragmas) to achieveruntime parallelism in the dataflow architecture. The source code 22 maygenerally use loops to perform various operations. Indeed, the runtimeperformance of applications may be dominated by the time spent inexecuting loops to perform tasks. On a dataflow architecture such asCSA, the performance of parallel loops may be accelerated by a) creatingmultiple copies of the loop bodies (e.g., “workers”), b) executing theworkers in parallel, and c) pipelining execution of the workers.

In the illustrated example, the source code 22 contains one or morelocal variables 26 (e.g., private variables), which lack dependenciesacross iterations of the loops in the source code 22. As will bediscussed in greater detail, such a variable might occur naturally whendeclared inside a loop. In an embodiment, the local variable(s) 26 areoccasionally used for relatively large data arrays. To improve thethroughput of the loops containing the local variable(s) 26 in such acase, the illustrated compiler 20 generates pipeline execution code 28for the local variable(s) 26 and incorporates the pipeline executioncode 28 into the output 24 of the compiler 20. Thus, the illustratedlocal variables are allocated in a way that each loop iteration gets itsown copy, thereby permitting pipelined execution. As already noted,pipelining execution of the workers may significantly enhanceperformance.

FIG. 2A shows source code 30 containing a loop (e.g., “for (int i=0;i<n; i++”) that declares a variable “b”, which may be considered a localvariable because it lacks dependencies across iterations of the loop. Inthe illustrated example, the variable has a fixed size (e.g., an arrayof 100 integers). Thus, the local storage requirements of the variable bare fixed and statically known to the compiler. The illustrated sourcecode 30 may be readily substituted for the source code 22 (FIG. 1),already discussed. Accordingly, pipeline execution code may beautomatically generated for the illustrated local variable.

FIG. 2B shows source code 32 containing a loop (e.g., “for (inti=ibegin; i<iend; i++)”) that declares a variable “spa”, which alsolacks dependencies across iterations of the loop and is considered alocal variable. In the illustrated example, the size of the variablevaries and is only known at runtime. The illustrated source code 32 maybe readily substituted for the source code 22 (FIG. 1), alreadydiscussed. Accordingly, pipeline execution code may be automaticallygenerated for the illustrated local variable.

FIG. 2C shows source code 34 containing a loop (e.g., “for (int j=x;j<y; j++)”) that uses a variable “b”, where the variable b is explicitlydesignated as a private variable (e.g., using the “private” clause).Other explicit clauses such as “firstprivate”, “lastprivate”,“reduction”, etc., may also be used. In the illustrated example, thevariable has a fixed size (e.g., an array of 100 integers). Thus, thelocal storage requirements of the variable b are fixed and staticallyknown to the compiler. The illustrated source code 34 may be readilysubstituted for the source code 22 (FIG. 1), already discussed.Accordingly, pipeline execution code may be automatically generated forthe illustrated local variable.

FIG. 2D shows source code 36 containing a loop (e.g., “for (int i=0;i<n; i++)”) that dynamically allocates memory for a variable “b” fromwithin the loop. In the illustrated example, the variable is a localvariable that lacks dependencies across iterations of the loop and thesize of the variable may either remain constant or vary. The illustratedsource code 36 may be readily substituted for the source code 22 (FIG.1), already discussed. Accordingly, pipeline execution code may beautomatically generated for the illustrated local variable.

Turning now to FIG. 3, a communication arc 40 (e.g., LIC) between afirst functional unit 42 (e.g., node) in a dataflow graph and a secondfunctional unit 44 in the dataflow graph is shown. In the illustratedexample, the functional units 42 and 44 are used to perform operationsin a loop on data associated with local variables. In an embodiment, thecommunication arc 40 includes buffer storage (not shown) such as, forexample, one or more line buffers, FIFO (first in first out) buffers,etc., which may be used to hold values that enable apportioning dataassociated with local variables in the loop to different loopiterations.

FIG. 4 shows a method 50 of operating a compiler. The method 50 maygenerally be implemented in a compiler such as, for example, thecompiler 20 (FIG. 1), already discussed. More particularly, the method50 may be implemented in one or more modules as a set of logicinstructions stored in a machine- or computer-readable storage mediumsuch as random access memory (RAM), read only memory (ROM), programmableROM (PROM), firmware, flash memory, etc., in configurable logic such as,for example, programmable logic arrays (PLAs), FPGAs, complexprogrammable logic devices (CPLDs), in fixed-functionality logichardware using circuit technology such as, for example, applicationspecific integrated circuit (ASIC), complementary metal oxidesemiconductor (CMOS) or transistor-transistor logic (TTL) technology, orany combination thereof.

For example, computer program code to carry out operations shown in themethod 50 may be written in any combination of one or more programminglanguages, including an object oriented programming language such asJAVA, SMALLTALK, C++ or the like and conventional procedural programminglanguages, such as the “C” programming language or similar programminglanguages. Additionally, logic instructions might include assemblerinstructions, instruction set architecture (ISA) instructions, machineinstructions, machine dependent instructions, microcode, state-settingdata, configuration data for integrated circuitry, state informationthat personalizes electronic circuitry and/or other structuralcomponents that are native to hardware (e.g., host processor, centralprocessing unit/CPU, microcontroller, etc.).

Illustrated processing block 52 provides for detecting one or more localvariables in source code, wherein the local variable(s) lackdependencies across iterations of a loop in the source code. The sourcecode may be associated with a communication channel as, for example, thecommunication arc 40 (FIG. 3) in a dataflow graph. In an embodiment,block 52 includes automatically parsing and/or searching the source codefor loops with fixed-size local storage (e.g., as in FIG. 2A),runtime-varying local storage (e.g., as in FIG. 2B), explicitlydesignated private variables (e.g., as in FIG. 2C), dynamicallyallocated local variables (e.g., as in FIG. 2D), and so forth. Moreover,block 52 may be conducted after a registerization of the source code.

Block 54 automatically generates (e.g., in response to the detection ofthe one or more local variables) pipeline execution code for the localvariable(s). As will be discussed in greater detail, block 54 mayinclude generating executable instructions to initialize a pool ofbuffer storage for the local variable(s), define a pipeline depth, anddefine a plurality of tokenized slots in the initialized pool of bufferstorage. In one example, the initialized pool of buffer storage isgreater than the local storage amount corresponding to a singleiteration of the loop. Moreover, each tokenized slot may correspond to apipelined iteration of the loop. Illustrated block 56 incorporates thepipeline execution code into the output of the compiler. The method 50therefore enhances performance by enabling the pipelining of loopscontaining private data, which improves throughput. Indeed, the overallcycles needed to execute a loop may be significantly less than theproduct of static loop cycles (e.g., the number of cycles needed toexecute one iteration of the loop) and the loop iteration count.

FIG. 5 shows a compiler 60 that may implement one or more aspects of themethod 50 (FIG. 4), already discussed. Additionally, the compiler 60 maybe readily substituted for the compiler 20 (FIG. 1), already discussed.In general, the compiler 60 enables pipelined execution of loopscontaining local variables and may be explained with reference to apiece of sample source code and compiler-generated pseudo-code. Forfurther reference, the end of this disclosure includes actualintermediate representation (IR) results using an LLVM compiler for asimilar sample before and after the principal compiler transformationsdescribed herein.

Using dynamically allocated local storage in a loop as an example, witha constant array size of 100 chosen for simplicity, it may be assumedthat the compiler 60 selects two workers for the loop and chooses apipeline depth of three for each worker loop.

An OpenMP language extension may also be implemented to allow explicitcontrol over worker creation and pipeline depth. Such an extension maybe considered optional.

The OpenMP language extension is:

  #pragma omp ... dataflow([num_workers[(<n>)]],[static](<chunksize>)]], [pipeline](<depth>)]])  for-loops

The pipeline(depth) sub-clause specifies how many loop iterations are tobe allowed to execute concurrently. The num_workers and static clausesspecify how many workers to create and the way to distribute the loopiterations across the workers. Other parallel annotation languagesand/or APIs (application programming interfaces) such as OpenACC,OpenCL, SYCL, etc., may also be used.

The solution for correctly handling private variables in pipelined loopsmay span many passes in the compiler 60. The transformations are inthree places as shown in FIG. 5:

A worker creation stage 62 may be used when local storage arises fromOpenMP clauses. In an embodiment, the worker creation stage 62 replacesOpenMP directives with expansions for multiple workers. The workercreation stage 62 may also represent local storage using dynamicallocation. Pseudocode for the worker creation stage 62 is providedbelow.

  Loop:  b = alloca ...  // the body of this loop references the localvariable b  ...  <inner j-loop>  ...  End-loop:

A local storage expansion stage 64 handles a relatively large portion ofthe transformations described herein. In one example, the local storageexpansion stage 64 handles allocation and referencing of privatevariables that remain. The pass of the illustrated stage 64 is conductedrelatively late to allow other compiler optimizations to registerizelocal variables as far as possible. Accordingly, variables that couldnot otherwise be registerized are dealt with in the stage 64. If a loophas a set S of private variables, then the stage 64 creates an array oftype S with dimension the pipeline depth, which is dynamic count ofiterations in flight.

A dataflow operation conversion stage 66 may handle the management ofthe individual slots in the private variable array created for eachloop.

Worker Creation

The worker creation stage 62 may create multiple workers as directed byOpenMP directives. For non-OpenMP loops, the worker creation stage 62may automatically decide the number of workers to generate. Similarly,OpenMP directives may specify the pipeline depth, or the compiler 60 mayselect the degree of pipelining to generate. For the purposes ofdiscussion, it is assumed that two workers are created and that apipeline depth of three is selected.

-   -   A pair of LLVM IR intrinsics may be introduced to support        loop-local storage:    -   r=pipeline.limited.entry(int id, int depth)        -   pipeline.limited.exit(r)

These intrinsics enclose the loops that need local storage. Thearguments of the “entry” call specify the pipeline depth and mark theplace where allocation for the enclosed loops occurs. The “exit” marksthe deallocation point. This representation ensures that independent ofthe number of workers generated, a single allocation/deallocation isdone for the loops.

Pseudo-code of the original single loop after the worker creation stage62 is shown below. In the illustrated example, the original loop hasbeen replicated to form two workers. Additionally, the local variable inthe original loop becomes a separate local variable in each of the newloops. Pipelining has not been accounted for yet and is done later inthe local storage expansion stage 64. The pseudo-code after processingby the worker creation stage 62 might be:

   depth.region = pipeline.limited.entry(id1, 3)  // Worker 0  region0 =parallel.region.entry(id2) Loop0:  b.priv.0 = alloca ...  // all uses ofb in the loop are replaced with b.priv.0  ...  <inner j-loop>  ...End-loop0:  parallel.region.exit(region0)  // Worker 1  region1 =parallel.region.entry(id3) Loop1:  b.priv.1 = alloca ...  // all uses ofb in the loop are replaced with b.priv.1  ...  <inner j-loop>  ...End-loop1:  parallel.region.exit(regionl) pipeline.limited.exit(depth.region)

Local Storage Expansion

In an embodiment, the local storage expansion stage 64 performs thetransformation to account for pipelining. The pipeline depth of three isenforced using the concept of a token and a pool of three token valuesis created for each worker. In one example, an iteration may begin whena token can be obtained from the pool. This operation is modeled by acall to “token.take”, which completes only when a local storage slotbecomes available. When an iteration is completed, the token is returnedto the pool. This return is modeled by a call to “token.return”. In oneexample, since only three distinct token values exist, only threeiterations can execute concurrently in each worker.

Pseudo-code after the local storage expansion stage 64 might be:

  // Local variable pool declaration #define num_workers 2 #define depth3 struct worker_pool {  struct loop_pool {   double B[100];  }ls[depth]; } pool[num_workers];  // Allocate the pool  pool =CsaMemAlloc(sizeof(worker_pool));  // Worker 0  w0 = &pool[0]; Loop0: // token.take will return one of these values:  // &w0.1s[0],&w0.1s[1], ..., w0.1s[depth-1]  w0_pool = token.take(w0, sizeof(ls),depth);  B_loop_local = &w0_pool.B;  // all uses of B in the loop arereplaced with B_loop_local  ...  <inner j-loop>  token.return(pool,w0_pool); End-loop0:  // Worker 1  w1 = &pool[1]; Loop 1:  // token.takewill return one of these values:  // &w1.1s[0], &w1.1s[1], ...,w1.1s[depth-1]  w1_pool = token.take(w1, sizeof(ls), depth); B_loop_local = &w1_pool.B;  // all uses of B in the loop are replacedwith B_loop_local  ...  <inner j-loop>  token.return(pool, w1_pool);End-loop 1:  // Deallocate the pool  CsaMemFree(pool);

Dataflow Operation Conversion

The final stage in implementing loop-local storage is during thedataflow operation conversion stage 66, which converts IR code intodataflow operations. The intrinsics token.take and token.return may beabstract representations of a mechanism that doles out a fixed number oftokens. In an embodiment, the physical implementation of this mechanismuses CSA LICs. The fundamental property of CSA LICs is to hold multiplevalues, to deliver values from one end of the LIC when read, and towrite values at the other end of the LIC when written. This property maybe used to permit only a fixed number of values to circulate through theloop body. In one example, the depth of the LIC is chosen to be theuser-specified pipeline depth. Additionally, the values in the LIC maybe offsets of individual slots allocated for the private variables of aloop. When a new iteration of the loop begins, a value is read from theLIC and added to a base address to generate the slot address for thecurrent iteration of the loop. When the iteration completes, the offsetmay be written back to the LIC. Because the LIC holds only “depth”number of values, only depth number of iterations may executeconcurrently, with each using a separate local storage slot. Exampledataflow operations that implement this scheme are shown below.

In a dataflow machine, instructions execute when their inputdependencies are satisfied. In the following, an “inord” is an inputordinal (e.g., a signal that an input dependence has been satisfied) andan “outord” is generated by an instruction when the instructioncompletes execution to indicate that the result in now available. Thegate64, add64 and mov instructions are explained first, and then theiruse in implementing token.take and token.return.

-   -   gate64 result, inord, value

The instruction does not execute until inord is available. Then, “value”becomes available as the result.

-   -   add64 result, input1, input2

The instruction does not execute until input1 and input2 are available.Then, “result” becomes available as the sum of “input1” and “input2”.

-   -   mov0 result, inord, value

The instruction does not execute until “inord” is available. Then,“value” becomes available as the result.

The pseudocode below is an example output of the dataflow operationconversion stage 66 for a CSA implementation.

// Each loop iteration requires 400 bytes of local storage // There are2 workers created for the original loop // A pipeline depth of 3 isimplemented // Total local storage = 400 * 3 * 2 bytes = 2400 bytes //Worker0 uses a pool that ranges from bytes 0 to 1199 // Worker1 uses apool that ranges from bytes 1200 to 2399 // Within each worker's pool,the 3 slots have offsets 0, 400, 800 // A LIC of depth 3 is initializedwith offset values: // offset_of(slot0), offset_of(slot1),offset_of(slot2) .lic@8 .i64 %slot_offset ... % slot_offset:ci64 =init64 0 % slot_offset:ci64 = init64 400 % slot_offset:ci64 = init64 800... ... // token_take implemented on CSA // Dynamic memory allocationoutside the loop generates the pool address pool = ...... // Equivalentof CsaMemAlloc(2400) ... // In the loop, when the token_take is ready toexecute //the pool address is made available to the add64 instructiongate64 pool_gated, token_take_inord, pool // The address of the localstorage slot assigned to this iteration // is computed add64slot_addr,_slot_offsets,_pool_gated .... .... // token_returnimplemented on CSA // In the loop, when the token_return is ready toexecute // The slot_offset is written back at the end of the LIC gate64slot_offsets, token_return_inord, slot_offsets // the completion oftoken_return is signaled with this mov0 mov0 token_return_outord,token_return inord

In this way, the dataflow properties of CSA LICs are exploited to enablepipelining of parallel loops while guaranteeing that enough localstorage is available for dynamic loop iterations. The compiler 60 mayconduct this transformation automatically and a prototype OpenMPlanguage extension has been implemented to demonstrate the advantages ofthe solution.

Turning now to FIG. 6, a performance-enhanced computing system 151 isshown. The system 151 may generally be part of an electronicdevice/platform having computing functionality (e.g., personal digitalassistant/PDA, notebook computer, tablet computer, convertible tablet,server), communications functionality (e.g., smart phone), imagingfunctionality (e.g., camera, camcorder), media playing functionality(e.g., smart television/TV), wearable functionality (e.g., watch,eyewear, headwear, footwear, jewelry), vehicular functionality (e.g.,car, truck, motorcycle), robotic functionality (e.g., autonomous robot),Internet of Things (IoT) functionality, etc., or any combinationthereof. In the illustrated example, the system 151 includes a hostprocessor 153 (e.g., central processing unit/CPU) having an integratedmemory controller (IMC) 155 that is coupled to a system memory 157.

The illustrated system 151 also includes an input output (10) module 159implemented together with the host processor 153 and a graphicsprocessor 161 (e.g., graphics processing unit/GPU) on a semiconductordie 163 as a system on chip (SoC). The illustrated IO module 159communicates with, for example, a display 165 (e.g., touch screen,liquid crystal display/LCD, light emitting diode/LED display), a networkcontroller 167 (e.g., wired and/or wireless), and mass storage 169(e.g., hard disk drive/HDD, optical disk, solid state drive/SSD, flashmemory).

In an embodiment, the host processor 153, the graphics processor 161and/or the IO module 159 execute instructions 171 retrieved from thesystem memory 157 and/or the mass storage 169 to perform one or moreaspects of the method 50 (FIG. 4), already discussed. Thus, execution ofthe illustrated instructions 171 may cause the computing system 151 todetect one or more local variables in source code, wherein the one ormore local variables lack dependencies across iterations of a loop inthe source code, automatically generate pipeline execution code for theone or more local variables, and incorporate the pipeline execution codeinto an output of a compiler.

In an embodiment, the pipeline execution code includes an initializationof a pool of buffer storage for the one or more local variables. In sucha case, the initialized pool of buffer storage may be greater than(e.g., several multiples of) a local storage amount corresponding to asingle iteration of the loop. Moreover, the pipelined execution code mayfurther include a definition of a plurality of tokenized slots in theinitialized pool of buffer storage, where each tokenized slotcorresponds to a pipelined iteration of the loop. In an embodiment, thepipelined execution code further includes a pipeline depth definition.In one example, the local variable(s) are detected after aregisterization of the source code and the source code is associatedwith a communication channel in a dataflow graph. Additionally, theautomatic generation of the pipeline execution code may be conducted inresponse to the detection of the local variable(s).

The illustrated system 151 is therefore performance-enhanced at least tothe extent that the pipelining of loops containing private data improvesthroughput. Indeed, the overall cycles needed to execute a loop may besignificantly less than the product of static loop cycles and the loopiteration count.

FIG. 7 shows a semiconductor package apparatus 173. The illustratedapparatus 173 includes one or more substrates 175 (e.g., silicon,sapphire, gallium arsenide) and logic 177 (e.g., transistor array andother integrated circuit/IC components) coupled to the substrate(s) 175.The logic 177 may be implemented at least partly in configurable logicor fixed-functionality logic hardware. In one example, the logic 177implements one or more aspects of the method 50 (FIG. 4), alreadydiscussed. Thus, the logic 177 may detect one or more local variables insource code, wherein the local variable(s) lack dependencies acrossiterations of a loop in the source code, automatically generate pipelineexecution code for the local variable(s), and incorporate the pipelineexecution code into an output of a compiler. The illustrated apparatus173 is therefore performance-enhanced at least to the extent that thepipelining of loops containing private data improves throughput. Indeed,the overall cycles needed to execute a loop may be significantly lessthan the product of static loop cycles and the loop iteration count.

In one example, the logic 177 includes transistor channel regions thatare positioned (e.g., embedded) within the substrate(s) 175. Thus, theinterface between the logic 177 and the substrate(s) 175 may not be anabrupt junction. The logic 177 may also be considered to include anepitaxial layer that is grown on an initial wafer of the substrate(s)175.

FIG. 8 illustrates a processor core 200 according to one embodiment. Theprocessor core 200 may be the core for any type of processor, such as amicro-processor, an embedded processor, a digital signal processor(DSP), a network processor, or other device to execute code. Althoughonly one processor core 200 is illustrated in FIG. 8, a processingelement may alternatively include more than one of the processor core200 illustrated in FIG. 8. The processor core 200 may be asingle-threaded core or, for at least one embodiment, the processor core200 may be multithreaded in that it may include more than one hardwarethread context (or “logical processor”) per core.

FIG. 8 also illustrates a memory 270 coupled to the processor core 200.The memory 270 may be any of a wide variety of memories (includingvarious layers of memory hierarchy) as are known or otherwise availableto those of skill in the art. The memory 270 may include one or morecode 213 instruction(s) to be executed by the processor core 200,wherein the code 213 may implement one or more aspects of the method 50(FIG. 4), already discussed. The processor core 200 follows a programsequence of instructions indicated by the code 213. Each instruction mayenter a front end portion 210 and be processed by one or more decoders220. The decoder 220 may generate as its output a micro operation suchas a fixed width micro operation in a predefined format, or may generateother instructions, microinstructions, or control signals which reflectthe original code instruction. The illustrated front end portion 210also includes register renaming logic 225 and scheduling logic 230,which generally allocate resources and queue the operation correspondingto the convert instruction for execution.

The processor core 200 is shown including execution logic 250 having aset of execution units 255-1 through 255-N. Some embodiments may includea number of execution units dedicated to specific functions or sets offunctions. Other embodiments may include only one execution unit or oneexecution unit that can perform a particular function. The illustratedexecution logic 250 performs the operations specified by codeinstructions.

After completion of execution of the operations specified by the codeinstructions, back end logic 260 retires the instructions of the code213. In one embodiment, the processor core 200 allows out of orderexecution but requires in order retirement of instructions. Retirementlogic 265 may take a variety of forms as known to those of skill in theart (e.g., re-order buffers or the like). In this manner, the processorcore 200 is transformed during execution of the code 213, at least interms of the output generated by the decoder, the hardware registers andtables utilized by the register renaming logic 225, and any registers(not shown) modified by the execution logic 250.

Although not illustrated in FIG. 8, a processing element may includeother elements on chip with the processor core 200. For example, aprocessing element may include memory control logic along with theprocessor core 200. The processing element may include I/O control logicand/or may include I/O control logic integrated with memory controllogic. The processing element may also include one or more caches.

Referring now to FIG. 9, shown is a block diagram of a computing system1000 embodiment in accordance with an embodiment. Shown in FIG. 9 is amultiprocessor system 1000 that includes a first processing element 1070and a second processing element 1080. While two processing elements 1070and 1080 are shown, it is to be understood that an embodiment of thesystem 1000 may also include only one such processing element.

The system 1000 is illustrated as a point-to-point interconnect system,wherein the first processing element 1070 and the second processingelement 1080 are coupled via a point-to-point interconnect 1050. Itshould be understood that any or all of the interconnects illustrated inFIG. 9 may be implemented as a multi-drop bus rather than point-to-pointinterconnect.

As shown in FIG. 9, each of processing elements 1070 and 1080 may bemulticore processors, including first and second processor cores (i.e.,processor cores 1074 a and 1074 b and processor cores 1084 a and 1084b). Such cores 1074 a, 1074 b, 1084 a, 1084 b may be configured toexecute instruction code in a manner similar to that discussed above inconnection with FIG. 8.

Each processing element 1070, 1080 may include at least one shared cache1896 a, 1896 b. The shared cache 1896 a, 1896 b may store data (e.g.,instructions) that are utilized by one or more components of theprocessor, such as the cores 1074 a, 1074 b and 1084 a, 1084 b,respectively. For example, the shared cache 1896 a, 1896 b may locallycache data stored in a memory 1032, 1034 for faster access by componentsof the processor. In one or more embodiments, the shared cache 1896 a,1896 b may include one or more mid-level caches, such as level 2 (L2),level 3 (L3), level 4 (L4), or other levels of cache, a last level cache(LLC), and/or combinations thereof.

While shown with only two processing elements 1070, 1080, it is to beunderstood that the scope of the embodiments is not so limited. In otherembodiments, one or more additional processing elements may be presentin a given processor. Alternatively, one or more of processing elements1070, 1080 may be an element other than a processor, such as anaccelerator or a field programmable gate array. For example, additionalprocessing element(s) may include additional processors(s) that are thesame as a first processor 1070, additional processor(s) that areheterogeneous or asymmetric to processor a first processor 1070,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessing element. There can be a variety of differences between theprocessing elements 1070, 1080 in terms of a spectrum of metrics ofmerit including architectural, micro architectural, thermal, powerconsumption characteristics, and the like. These differences mayeffectively manifest themselves as asymmetry and heterogeneity amongstthe processing elements 1070, 1080. For at least one embodiment, thevarious processing elements 1070, 1080 may reside in the same diepackage.

The first processing element 1070 may further include memory controllerlogic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078.Similarly, the second processing element 1080 may include a MC 1082 andP-P interfaces 1086 and 1088. As shown in FIG. 9, MC's 1072 and 1082couple the processors to respective memories, namely a memory 1032 and amemory 1034, which may be portions of main memory locally attached tothe respective processors. While the MC 1072 and 1082 is illustrated asintegrated into the processing elements 1070, 1080, for alternativeembodiments the MC logic may be discrete logic outside the processingelements 1070, 1080 rather than integrated therein.

The first processing element 1070 and the second processing element 1080may be coupled to an I/O subsystem 1090 via P-P interconnects 1076 1086,respectively. As shown in FIG. 9, the I/O subsystem 1090 includes P-Pinterfaces 1094 and 1098. Furthermore, I/O subsystem 1090 includes aninterface 1092 to couple I/O subsystem 1090 with a high performancegraphics engine 1038. In one embodiment, bus 1049 may be used to couplethe graphics engine 1038 to the I/O subsystem 1090. Alternately, apoint-to-point interconnect may couple these components.

In turn, I/O subsystem 1090 may be coupled to a first bus 1016 via aninterface 1096. In one embodiment, the first bus 1016 may be aPeripheral Component Interconnect (PCI) bus, or a bus such as a PCIExpress bus or another third generation I/O interconnect bus, althoughthe scope of the embodiments are not so limited.

As shown in FIG. 9, various I/O devices 1014 (e.g., biometric scanners,speakers, cameras, sensors) may be coupled to the first bus 1016, alongwith a bus bridge 1018 which may couple the first bus 1016 to a secondbus 1020. In one embodiment, the second bus 1020 may be a low pin count(LPC) bus. Various devices may be coupled to the second bus 1020including, for example, a keyboard/mouse 1012, communication device(s)1026, and a data storage unit 1019 such as a disk drive or other massstorage device which may include code 1030, in one embodiment. Theillustrated code 1030 may implement one or more aspects of the method 50(FIG. 4), already discussed. Further, an audio I/O 1024 may be coupledto second bus 1020 and a battery 1010 may supply power to the computingsystem 1000.

Note that other embodiments are contemplated. For example, instead ofthe point-to-point architecture of FIG. 9, a system may implement amulti-drop bus or another such communication topology. Also, theelements of FIG. 9 may alternatively be partitioned using more or fewerintegrated chips than shown in FIG. 9.

Additional Notes and Examples

Example 1 includes a performance-enhanced computing system comprising anetwork controller, a processor coupled to the network controller, and amemory coupled to the processor, the memory including a set ofexecutable program instructions, which when executed by the processor,cause the processor to detect one or more local variables in sourcecode, wherein the one or more local variables lack dependencies acrossiterations of a loop in the source code, automatically generate pipelineexecution code for the one or more local variables, and incorporate thepipeline execution code into an output of the compiler.

Example 2 includes the computing system of Example 1, wherein thepipeline execution code is to include an initialization of a pool ofbuffer storage for the one or more local variables.

Example 3 includes the computing system of Example 2, wherein theinitialized pool of buffer storage is to be greater than a local storageamount corresponding to a single iteration of the loop.

Example 4 includes the computing system of Example 2, wherein thepipeline execution code is to further include a definition of aplurality of tokenized slots in the initialized pool of buffer storage,and wherein each tokenized slot is to correspond to a pipelinediteration of the loop.

Example 5 includes the computing system of Example 1, wherein thepipeline execution code is to include a pipeline depth definition.

Example 6 includes the computing system of any one of Examples 1 to 5,wherein the one or more local variables are to be detected after aregisterization of the source code, automatic generation of the pipelineexecution code is to be in response to detection of the one or morelocal variables, and the source code is to be associated with acommunication channel in a dataflow graph.

Example 7 includes a semiconductor apparatus comprising one or moresubstrates, and logic coupled to the one or more substrates, wherein thelogic is implemented at least partly in one or more of configurablelogic or fixed-functionality hardware logic, the logic coupled to theone or more substrates to detect one or more local variables in sourcecode, wherein the one or more local variables lack dependencies acrossiterations of a loop in the source code, automatically generate pipelineexecution code for the one or more local variables, and incorporate thepipeline execution code into an output of a compiler.

Example 8 includes the semiconductor apparatus of Example 7, wherein thepipeline execution code is to include an initialization of a pool ofbuffer storage for the one or more local variables.

Example 9 includes the semiconductor apparatus of Example 8, wherein theinitialized pool of buffer storage is to be greater than a local storageamount corresponding to a single iteration of the loop.

Example 10 includes the semiconductor apparatus of Example 8, whereinthe pipeline execution code is to further include a definition of aplurality of tokenized slots in the initialized pool of buffer storage,and wherein each tokenized slot is to correspond to a pipelinediteration of the loop.

Example 11 includes the semiconductor apparatus of Example 7, whereinthe pipeline execution code is to include a pipeline depth definition.

Example 12 includes the semiconductor apparatus of any one of Examples 7to 11, wherein the one or more local variables are to be detected aftera registerization of the source code, automatic generation of thepipeline execution code is to be in response to detection of the one ormore local variables, and the source code is to be associated with acommunication channel in a dataflow graph.

Example 13 includes the semiconductor apparatus of any one of Examples 7to 12, wherein the logic coupled to the one or more substrates includestransistor channel regions that are positioned within the one or moresubstrates.

Example 14 includes at least one computer readable storage mediumcomprising a set of instructions, which when executed by a computingsystem, cause the computing system to detect one or more local variablesin source code, wherein the one or more local variables lackdependencies across iterations of a loop in the source code,automatically generate pipeline execution code for the one or more localvariables, and incorporate the pipeline execution code into an output ofa compiler.

Example 15 includes the at least one computer readable storage medium ofExample 14, wherein the pipeline execution code is to include aninitialization of a pool of buffer storage for the one or more localvariables.

Example 16 includes the at least one computer readable storage medium ofExample 15, wherein the initialized pool of buffer storage is to begreater than a local storage amount corresponding to a single iterationof the loop.

Example 17 includes the at least one computer readable storage medium ofExample 15, wherein the pipeline execution code is to further include adefinition of a plurality of tokenized slots in the initialized pool ofbuffer storage, and wherein each tokenized slot is to correspond to apipelined iteration of the loop.

Example 18 includes the at least one computer readable storage medium ofExample 14, wherein the pipeline execution code is to include a pipelinedepth definition.

Example 19 includes the at least one computer readable storage medium ofany one of Examples 14 to 18, wherein the one or more local variablesare to be detected after a registerization of the source code, automaticgeneration of the pipeline execution code is to be in response todetection of the one or more local variables, and the source code is tobe associated with a communication channel in a dataflow graph.

Example 20 includes a method of operating a compiler, the methodcomprising detecting one or more local variables in source code, whereinthe one or more local variables lack dependencies across iterations of aloop in the source code, automatically generating pipeline executioncode for the one or more local variables, and incorporating the pipelineexecution code into an output of the compiler.

Example 21 includes the method of Example 20, wherein the pipelineexecution code includes an initialization of a pool of buffer storagefor the one or more local variables.

Example 22 includes the method of Example 21, wherein the initializedpool of buffer storage is to be greater than a local storage amountcorresponding to a single iteration of the loop.

Example 23 includes the method of Example 21, wherein the pipelineexecution code further includes a definition of a plurality of tokenizedslots in the initialized pool of buffer storage, and wherein eachtokenized slot is to correspond to a pipelined iteration of the loop.

Example 24 includes the method of Example 20, wherein the pipelineexecution code includes a pipeline depth definition.

Example 25 includes the method of any one of Examples 20 to 24, whereinthe one or more local variables are detected after a registerization ofthe source code, automatic generation of the pipeline execution code isin response to detection of the one or more local variables, and thesource code is associated with a communication channel in a dataflowgraph.

Example 26 includes means for performing the method of any one ofExamples 20 to 25.

Thus, technology described herein may include an automated compilertransformation that can take as input a loop that has some form of localloop storage and dynamically pipeline the loop using one or more workersfor a dataflow architecture such as CSA. The compiler may detect localstorage remaining in loops after registerization and allocate enoughmemory to hold the private variables for a) each worker, and b) eachconcurrent execution of a worker. As each worker body commencesexecution, the worker body may be assigned a unique slot in theallocated private storage. When the worker completes execution of aniteration, the local storage slot associated with the worker may beautomatically recycled for use in future iterations.

Several applications/benchmarks such as, for example, the SPGemm (sparsematrix-matrix multiplication) and Apriori benchmarks, may benefit fromthe transformation technology described herein.

Embodiments are applicable for use with all types of semiconductorintegrated circuit (“IC”) chips. Examples of these IC chips include butare not limited to processors, controllers, chipset components,programmable logic arrays (PLAs), memory chips, network chips, systemson chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, insome of the drawings, signal conductor lines are represented with lines.Some may be different, to indicate more constituent signal paths, have anumber label, to indicate a number of constituent signal paths, and/orhave arrows at one or more ends, to indicate primary information flowdirection. This, however, should not be construed in a limiting manner.Rather, such added detail may be used in connection with one or moreexemplary embodiments to facilitate easier understanding of a circuit.Any represented signal lines, whether or not having additionalinformation, may actually comprise one or more signals that may travelin multiple directions and may be implemented with any suitable type ofsignal scheme, e.g., digital or analog lines implemented withdifferential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, althoughembodiments are not limited to the same. As manufacturing techniques(e.g., photolithography) mature over time, it is expected that devicesof smaller size could be manufactured. In addition, well knownpower/ground connections to IC chips and other components may or may notbe shown within the figures, for simplicity of illustration anddiscussion, and so as not to obscure certain aspects of the embodiments.Further, arrangements may be shown in block diagram form in order toavoid obscuring embodiments, and also in view of the fact that specificswith respect to implementation of such block diagram arrangements arehighly dependent upon the computing system within which the embodimentis to be implemented, i.e., such specifics should be well within purviewof one skilled in the art. Where specific details (e.g., circuits) areset forth in order to describe example embodiments, it should beapparent to one skilled in the art that embodiments can be practicedwithout, or with variation of, these specific details. The descriptionis thus to be regarded as illustrative instead of limiting.

The term “coupled” may be used herein to refer to any type ofrelationship, direct or indirect, between the components in question,and may apply to electrical, mechanical, fluid, optical,electromagnetic, electromechanical or other connections. In addition,the terms “first”, “second”, etc. may be used herein only to facilitatediscussion, and carry no particular temporal or chronologicalsignificance unless otherwise indicated.

As used in this application and in the claims, a list of items joined bythe term “one or more of” may mean any combination of the listed terms.For example, the phrases “one or more of A, B or C” may mean A; B; C; Aand B; A and C; B and C; or A, B and C.

Those skilled in the art will appreciate from the foregoing descriptionthat the broad techniques of the embodiments can be implemented in avariety of forms. Therefore, while the embodiments have been describedin connection with particular examples thereof, the true scope of theembodiments should not be so limited since other modifications willbecome apparent to the skilled practitioner upon a study of thedrawings, specification, and following claims.

We claim:
 1. A computing system comprising: a network controller; aprocessor coupled to the network controller; and a memory coupled to theprocessor, the memory including a set of executable programinstructions, which when executed by the processor, cause the processorto: detect one or more local variables in source code, wherein the oneor more local variables lack dependencies across iterations of a loop inthe source code, automatically generate pipeline execution code for theone or more local variables, wherein the pipeline execution code is toinclude an initialization of a pool of buffer storage for the one ormore local variables, wherein the pipeline execution code is to includea definition of a plurality of tokenized slots in the initialized poolof buffer storage, and wherein the tokenized slots are to correspond toa number of pipelined iterations of the loop that are to execute inparallel with each other, and incorporate the pipeline execution codeinto an output of a compiler.
 2. The computing system of claim 1,wherein the initialized pool of buffer storage is to be greater than alocal storage amount corresponding to a single iteration of the loop. 3.The computing system of claim 1, wherein each tokenized slot is tocorrespond to a pipelined iteration of the loop.
 4. The computing systemof claim 1, wherein the pipeline execution code is to include a pipelinedepth definition.
 5. The computing system of claim 1, wherein the one ormore local variables are to be detected after a registerization of thesource code, automatic generation of the pipeline execution code is tobe in response to detection of the one or more local variables, and thesource code is to be associated with a communication channel in adataflow graph.
 6. A semiconductor apparatus comprising: one or moresubstrates; and logic coupled to the one or more substrates, wherein thelogic is implemented at least partly in one or more of configurablelogic or fixed-functionality hardware logic, the logic coupled to theone or more substrates to: detect one or more local variables in sourcecode, wherein the one or more local variables lack dependencies acrossiterations of a loop in the source code; automatically generate pipelineexecution code for the one or more local variables, wherein the pipelineexecution code is to include an initialization of a pool of bufferstorage for the one or more local variables, wherein the pipelineexecution code is to include a definition of a plurality of tokenizedslots in the initialized pool of buffer storage, and wherein thetokenized slots are to correspond to a number of pipelined iterations ofthe loop that are to execute in parallel with each other; andincorporate the pipeline execution code into an output of a compiler. 7.The semiconductor apparatus of claim 6, wherein the initialized pool ofbuffer storage is to be greater than a local storage amountcorresponding to a single iteration of the loop.
 8. The semiconductorapparatus of claim 6, wherein each tokenized slot is to correspond to apipelined iteration of the loop.
 9. The semiconductor apparatus of claim6, wherein the pipeline execution code is to include a pipeline depthdefinition.
 10. The semiconductor apparatus of claim 6, wherein the oneor more local variables are to be detected after a registerization ofthe source code, automatic generation of the pipeline execution code isto be in response to detection of the one or more local variables, andthe source code is to be associated with a communication channel in adataflow graph.
 11. The semiconductor apparatus of claim 6, wherein thelogic coupled to the one or more substrates includes transistor channelregions that are positioned within the one or more substrates.
 12. Atleast one non-transitory computer readable storage medium comprising aset of instructions, which when executed by a computing system, causethe computing system to: detect one or more local variables in sourcecode, wherein the one or more local variables lack dependencies acrossiterations of a loop in the source code; automatically generate pipelineexecution code for the one or more local variables, wherein the pipelineexecution code is to include an initialization of a pool of bufferstorage for the one or more local variables, wherein the pipelineexecution code is to include a definition of a plurality of tokenizedslots in the initialized pool of buffer storage, and wherein thetokenized slots are to correspond to a number of pipelined iterations ofthe loop that are to execute in parallel with each other; andincorporate the pipeline execution code into an output of a compiler.13. The at least one non-transitory computer readable storage medium ofclaim 12, wherein the initialized pool of buffer storage is to begreater than a local storage amount corresponding to a single iterationof the loop.
 14. The at least one non-transitory computer readablestorage medium of claim 12, wherein each tokenized slot is to correspondto a pipelined iteration of the loop.
 15. The at least onenon-transitory computer readable storage medium of claim 12, wherein thepipeline execution code is to include a pipeline depth definition. 16.The at least one non-transitory computer readable storage medium ofclaim 12, wherein the one or more local variables are to be detectedafter a registerization of the source code, automatic generation of thepipeline execution code is to be in response to detection of the one ormore local variables, and the source code is to be associated with acommunication channel in a dataflow graph.
 17. A method comprising:detecting one or more local variables in source code, wherein the one ormore local variables lack dependencies across iterations of a loop inthe source code; automatically generating pipeline execution code forthe one or more local variables, wherein the pipeline execution codeincludes an initialization of a pool of buffer storage for the one ormore local variables, wherein the pipeline execution code includes adefinition of a plurality of tokenized slots in the initialized pool ofbuffer storage, and wherein the tokenized slots correspond to a numberof pipelined iterations of the loop that will execute in parallel witheach other; and incorporating the pipeline execution code into an outputof a compiler.
 18. The method of claim 17, wherein the initialized poolof buffer storage is to be greater than a local storage amountcorresponding to a single iteration of the loop.
 19. The method of claim17, wherein each tokenized slot is to correspond to a pipelinediteration of the loop.
 20. The method of claim 17, wherein the pipelineexecution code includes a pipeline depth definition.
 21. The method ofclaim 17, wherein the one or more local variables are detected after aregisterization of the source code, automatic generation of the pipelineexecution code is in response to detection of the one or more localvariables, and the source code is associated with a communicationchannel in a dataflow graph.